Alif Semiconductor /AE722F80F55D5LS_CM55_HE_View /DSI /DSI_TO_CNT_CFG

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Interpret as DSI_TO_CNT_CFG

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0LPRX_TO_CNT0HSTX_TO_CNT

Description

Timeout Counter Configuration Register

Fields

LPRX_TO_CNT

This field configures the timeout counter that triggers a low-power reception timeout contention detection (measured in DSI_CLKMGR_CFG[TO_CLK_DIVISION] cycles).

HSTX_TO_CNT

This field configures the timeout counter that triggers a high-speed transmission timeout contention detection (measured in DSI_CLKMGR_CFG[TO_CLK_DIVISION] cycles). If using non-burst mode and there is not sufficient time to switch from high-speed to low-power and back in the period which is from one line data finishing to the next line sync start, the DSI link returns low-power state once per frame, then the DSI_CLKMGR_CFG[TO_CLK_DIVISION] and HSTX_TO_CNT fields should be configured to satisfy the following formula: HSTX_TO_CNT x LANEBYTECLK_period x TO_CLK_DIVISION >= the time of one FRAME data transmission x (1 + 10%) In burst mode, RGB pixel packets are time-compressed, leaving more time during a scan line. So if in burst mode and there is sufficient time to switch from high-speed to low-power and back in the period of time from one line data finishing to the next line sync start, the DSI link can return low-power mode and back in this time interval to save power. If this case, the DSI_CLKMGR_CFG[TO_CLK_DIVISION] and HSTX_TO_CNT fields should be configured to satisfy the following formula: HSTX_TO_CNT x LANEBYTECLK_period x TO_CLK_DIVISION >= the time of one LINE data transmission x (1 + 10%)

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